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Your search returned 24 records. Click on the hyperlinks to view further details of Titles.. |
Magazine Name : Ieee Journal Of Solid-State Circuits
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Year : 2000 Volume number : 35 Issue: 11 |
A Third-Generation Sparc V9 64-B Microprocessor
(Article)
Subject:
Computer Architecture
,
Cmos Integrated Circuits
,
High-Speed Integrated Circuits
,
Integrated Circuit Design
Author:
Raymond
Heald
page:
1526
-
1538
The First Ia-64 Microprocessor
(Article)
Subject:
Clock Deskew
,
Design For Test
,
Explicitly Parallel Instruction Computing
,
Ia-64
Author:
Stefan
Rusu
Gadi
Singer
page:
1539
-
1544
Clock Generation And Distribution For The First Ia-64 Microprocessor
(Article)
Subject:
Active Deskew
,
Clock
,
Clock Distribution
,
Clock Generation
Author:
Simon
Tam
Stefan
Rusu
page:
1545
-
1552
Active Ghz Clock Network Using Distributed Plls
(Article)
Subject:
Clock Networks
,
Multiple Oscillator System
,
Phase Locked Loop (Pll)
Author:
Vadim
Gutnik
Anantha P
Chandrakasan
page:
1553
-
1560
The Design And Implementation Of A Low-Power Clock-Powered Microprocessor
(Article)
Subject:
Implementation
,
Low-Power
,
Microprocessor
Author:
William
Athas
Nestoras
Tzartzanis
page:
1561
-
1570
A Dynamic Voltage Scaled Microprocessor System
(Article)
Subject:
Adaptive Processor
,
Energy Efficient
,
Low Power
,
Variable Voltage
Author:
Thomas D.
Burd
Trevor A.
Pering
page:
1571
-
1580
A 1.3-Cycle Lock Time, Non-Pll/Dll Clock Multiplier Based On Direct Clock Cycle Interpolation For "Clock On Demand"
(Article)
Subject:
Csd
,
Dll
,
Interpolator
,
Lock Time
Author:
Takanori
Saeki
Masafumi
Mitsuishi
page:
1581
-
1590
Low-Power Area-Efficient High-Speed I/O Circuit Techniques
(Article)
Subject:
Delay-Locked Loop
,
Equalization
,
I/O Circuit
,
Offset-Cancellation
Author:
Ming-Ju Edward
Lee
page:
1591
-
1599
A Variable-Frequency Parallel I/O Interface With Adaptive Power-Supply Regulation
(Article)
Subject:
Adaptive Control
,
Data Communication
,
Dc-Dc Power Conversion
,
Delay-Locked Loops
Author:
Gu-Yeon
Wei
Jaeha
Kim
page:
1600
-
1610
A 20-Gb/S Cmos Multichannel Transmitter And Receiver Chip Set For Ultra-High-Resolution Digital Displays
(Article)
Subject:
8b10b
,
10b8b
,
Receiver
,
Transmitter
Author:
Muneo
Fukaishi
Kazuyuki
Nakamura
page:
1611
-
1618
A 2.4 Gb/S/Pin Simultaneous Bidirectional Parallel Link With Per-Pin Skew Compensation
(Article)
Subject:
Parallel Links
,
Simultaneous Bidirectional Links
,
Single-Ended Links
,
Skew Compensation
Author:
Evelina
Yeung
Mark A
Horowitz
page:
1619
-
1628
A 16-Mb 400-Mhz Loadless Cmos Four-Transistor Sram Macro
(Article)
Subject:
Cmos Memory Integrated Circuits
,
Sram Chips
Author:
Koichi
Takeda
page:
1631
-
1640
An 833-Mhz 1.5-W 18-Mb Cmos Sram With 1.67 Gb/S/Pin
(Article)
Subject:
Cmos Active Pixel
,
Sram
Author:
Harold
Pilo
Archie
Allen
page:
1641
-
1647
A Channel-Erasing 1.8-V-Only 32-Mb Nor Flash Eeprom With A Bitline Direct Sensing Scheme
(Article)
Subject:
Channel Erase
,
Bitline
Author:
Shigeru
Atsumi
page:
1648
-
1654
40-Mm2 3-V-Only 50-Mhz 64-Mb 2-B/Cell Che Nor Flash Memory
(Article)
Subject:
Balanced/Unbalanced Sensing Scheme
,
Burst Read
,
Error Correction Codes
,
Multilevel Cell
Author:
Giovanni
Campardo
page:
1655
-
1667
An 8-Ns Random Cycle Embedded Ram Macro With Dual-Port Interleaved Dram Architecture (D2ram)
(Article)
Subject:
Dual-Port
,
Embedded Dram
,
Open Bitline
,
Pipelined Operation
Author:
Yasuhiro
Agata
page:
1668
-
1672
1-Ghz Fully Pipelined 3.7-Ns Address Access Time 8k 8 1024 Embedded Synchronous Dram Macro
(Article)
Subject:
1-Ghz Synchronous E-Dram
,
3.7-Ns Access Time
,
Embedded Dram
,
Pipelined
Author:
Osamu
Takahashi
page:
1673
-
1679
A 0.4-Um 3.3-V 1t1c 4-Mb Nonvolatile Ferroelectric Ram With Fixed Bitline Reference Voltage Scheme And Data Protection Circuit
(Article)
Subject:
Nonvolatile
,
Ferroelectric
,
Bitline
Author:
Byung-Gil
Jeon
Mun-Kyu
Choi
page:
1690
-
1694
A 1-V Heterogeneous Reconfigurable Dsp Ic For Wireless Baseband Digital Signal Processing
(Article)
Subject:
Digital Signal Processors
,
Energy Conservation
,
Field-Programmable Gate Array (Fpga) Emulation
,
Reconfigurable Architectures
Author:
Hui
Zhang
Vandana
Prabhu
page:
1697
-
1704
A 660-Uw 50-Mops 1-V Dsp For A Hearing Aid Chip Set
(Article)
Subject:
Algorithm Optimization
,
Digital Signal Processing
,
Gated Clock Techniques
,
Low Power Design
Author:
Philippe
Mosch
page:
1705
-
1712
A 60-Mhz 240-Mw Mpeg-4 Videophone Lsi With 16-Mb Embedded Dram
(Article)
Subject:
Videophone
,
Embedded Dram
Author:
Masafumi
Takahashi
page:
1713
-
1721
Heterogeneous Multiprocessor For The Management Of Real-Time Video And Graphics Streams
(Article)
Subject:
Heterogeneous Multiprocessor
,
Management
,
Real-Time
Author:
Marino T. J.
Strik
page:
1722
-
1731
A 30-Frames/S Megapixel Real-Time Cmos Image Processor
(Article)
Subject:
1-Ccd Camera
,
Autofocus
,
Color Space Transformation
,
Dark Current
Author:
Daniel
Doswald
page:
1732
-
1743
A Parallel Vector-Quantization Processor Eleminating Redundant Calculations For Real-Time Motion Picture Compression
(Article)
Subject:
Image Compression
,
Low Bit-Rate Video Compression
,
Parallel Processing
,
Vector Quantization
Author:
Toshiyuki
Nozawa
page:
1744
-
1751
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